1. Field of the Invention
The present invention relates to a boosting circuit, and more particularly to a boosting circuit that compensates for voltage fluctuation due to operation of load.
2. Description of the Background Art
A semiconductor memory device called a DRAM (dynamic random access memory) is formed using primarily a CMOS process. A memory cell transistor being a component thereof is often formed with a MOS transistor of only an N channel type to reduce chip area. To accurately write data at an H (logical high) level into a memory cell, a voltage that is higher than a normal H level or power supply voltage level (hereinafter, referred to as a "boosted voltage") is supplied to the gate of the memory cell transistor. When a threshold voltage of the memory cell transistor is expressed as Vthc and a voltage level of data at the H level to be written into the memory cell as VccS, this boosted voltage Vpp can be expressed as EQU Vpp=VccS+Vthc+.alpha..
Here, .alpha. represents a margin.
This boosted voltage Vpp cannot be set at a large value from the standpoint of the breakdown voltage of gate oxide film in the memory cell transistor. In addition, in the case where EQU boosted voltage Vpp&lt;VccS+Vthc(.alpha.&lt;0),
data at the H level cannot be written back to the memory cell completely. In view of the foregoing, in the case where the internal power supply voltage VccS is 2.0V and the thickness of oxide film of the memory cell transistor is 70 .ANG., for example, it is reasonable to set boosted voltage Vpp on the order of 3.5V. Normally, the boosted voltage Vpp is generated in a boosting circuit formed on the same chip. The level of boosted voltage Vpp is monitored within the chip, and the boosting circuit is configured to operate when it drops below its prescribed set level to maintain the boosted voltage Vpp at the set level.
FIG. 7 is a block diagram showing an exemplary configuration of such boosting circuit. It should be understood that the boosting circuit shown in FIG. 7 is identical to the one illustrated in Ultra LSI Memory (by Kiyoo Ito, Baifukan, 1994, p.317, FIG. 4.56). In this circuit, the voltage level of the boosted voltage Vpp is detected by a level monitor LM, and when the level of detected boosted voltage Vpp is lower than a prescribed detection level, a ring oscillator RS starts to operate, and in response, a pumping capacitor Cp in a booster circuit BC is driven. As a result, the level of boosted voltage Vpp increases. When the level of boosted voltage Vpp reaches the prescribed level, level monitor LM causes ring oscillator RS to stop operation, and thus, pumping capacitor Cp finishes boosting.
In a conventional boosting circuit, one detection level has been set in advance, and whether to operate the boosting circuit or not is determined depending on whether the level of boosted voltage is lower than the detection level or not. In such boosting circuit, however, even when the boosted voltage Vpp is only slightly below the detection level, boosted voltage Vpp is unnecessarily increased, because boosted voltage Vpp is boosted by booster circuit BC having a large driving capability, or, due to a response lag of level monitor LM per se. This results in boosted voltage Vpp that appears to fluctuate in a large amount with respect to a desired set voltage. Further, since the boosting capability of booster circuit BC is designed based on the minimal cycle of DRAM in a general specification, booster circuit BC having a large driving capability is used to conduct boosting even when the DRAM is operating in an extremely slow cycle. This leads to unnecessary voltage fluctuation. These situations are undesirable from the standpoints that the upper limit of boosted voltage is set because of its reliability, and the lower limit is set to write data at an H level in a stable state.
To smooth out the fluctuation of boosted voltage due to the operation of boosting circuit as described above, there has been proposed a solution to insert a capacitor between a boosted node receiving the boosted voltage and a ground node. It is difficult, however, to insert such capacitor having an extremely large capacitance in the modern art where further downscaling of chip size has been required.